The present invention relates to a semiconductor device which is optimal to provide a large wafer area and a large number of functions formed on the wafer or less number of parts to be fabricated, and a method for fabricating it. The semiconductor device according to the present invention is suitable to realize a large capacity and high performance.
Heretofore, a semiconductor device has been required to have plural functions such as functions of arithmetic, storage and input/output on its monolithic chip. But an increase in the chip area leads to a considerable reduction in the fabrication yield so that such requirement has been dealt with by curtailing each function and reducing the area occupied by each function.
Thus, the semiconductor device has been constructed with each function made lower than the case where a single chip has a single function. Its one example is the Hitachi xe2x80x9cHD 401220xe2x80x9d which is an; eight-bit single chip microcomputer described in HITACHI MICROCOMPUTER GENERAL USER""S GUIDE Feb. 1991 page 121.
This microcomputer has many functions including a 2048-byte ROM, 32-byte EEPROM, timer, D/A converter and I/O port. The performance of each function is inferior to that in the system including the Hitachi xe2x80x9cHD 64180xe2x80x9d which is an; eight-bit microcomputer and the Hitachi xe2x80x9cHM 514102xe2x80x9dwhich is a 4 megabyte DRAM. The technology of combining plural chips to form a single semiconductor device is disclosed in JP-A-2-184063.
The former technology, in which each function is made lower than in the case of the single-chip single-function, is not suitable to the case where upgraded functions are required.
The latter technology, in which the gaps necessarily generated between chips are filled with resin, cannot be applicable to a high temperature process. The reason why the gaps are generated is that the chips etched by isotropic etching or insufficient anisotropic etching are combined.
Conventional defect relief technology for LSI with the scale of a semiconductor substrate is disclosed in e.g. (1) xe2x80x9cNIKKEI MICRODEVICExe2x80x9d April 1986, pages 45-46 issued Apr. 1, 1986 by Nikkei McGraw-Hill Inc., and (2) JP-A-62-147746.
The reference (1) makes an explanation of the defect relief technology for the integrated circuit with the scale of a substrate. Its summary is as follows. First, poor device areas of device areas on the substrate are removed, and at the removed areas planar square holes each penetrating from the principal surface of the substrate to the back surface thereof are formed. Secondly, the substrate, under the state where the principal surface is directed downward, is placed on a prescribed pedestal. Subsequently, defect-free semi-conductor elements chips, under the state where their principal surface is directed downward, are inserted or mounted in the holes. The size of the defect-free element chips inserted in the holes is e.g. 4.99 mm square or so. Thereafter, the gaps between the defect-free element chips and the substrate are filled with resin such as epoxy resin. Finally, the substrate is turned over and wirings are made between the pads of the defect-free element chips and those for the defect-free areas on the substrate, thus completing the integrated circuit.
The reference (2) also describes a defect relief technique for integrated circuits. Like the reference (1), in this technique also, defective element areas on a substrate are removed and defect-free element chips are inserted in the removed areas; thereafter wirings are made between the element chips to complete an integrated circuit.
In recent years, semiconductor devices have been advanced to provide large capacity and upgraded function. Also the element chips included in the device have advanced to provide upgraded function and large size. But if the element chips are made large-sized, the number of element areas which can be formed on the substrate will be reduced. In addition, if the element chips are made large-sized and also highly integrated, the defect production rate will be increased owing to alien substances. As a result, the number of defect-free element chips which can be acquired from a single substrate will be greatly decreased.
Thus, it is expected that realizing the large capacity and upgraded function of the semiconductor device makes it very difficult to assure the element production yield profitable in cost. The method which may reduce the number of defect-free element chips which can be acquired from a single semiconductor substrate to one or less cannot be used for the production of the semiconductor device. From such a standpoint, as a future trend of the semiconductor devices, an important problem to be solved is to provide a method of fabricating a semiconductor device with high production yield or realizing defect relief with high reliability.
Further, in recent years, development and fabrication of custom products for semiconductor devices have advanced. The custom products are fabricated in accordance with the specification requested by a user by the number required by him. Thus, the number of the kinds of products is increased whereas the number of products for each kind is not increased. As a result, reduction in the production cost for the products due to mass-production cannot be expected. The cost of the products will greatly depend on the element production yield. In order to assure the element yield profitable in cost, the defect relief technique with high reliability is required as in the above case.
In the conventional techniques disclosed in the above references (1) and (2), defective element chips cannot be easily removed and defect-free element chips cannot be precisely positioned when they are to be mounted on a substrate so that the wiring method of connecting the elements with the substrate is problematic. The conventional techniques, as they are, cannot be adopted as relief technique for elements.
An object of the present invention is to. provide a method for fabricating a large-sized semi-conductor device with high yield and a highly reliable defect relief technique for it.
Another object of the present invention is to provide a semiconductor device with plural functions which are formed on a single chip and not inferior to those in the case of a single-chip single-function.
Still another object of the present invention is to provide a semiconductor device which can grant a user""s request of desiring to fabricate the semiconductor device at low cost although the production amount thereof is little and can be fabricated at low cost without deteriorating the function.
A further object of the present invention is to provide a semiconductor device which is applicable to a high temperature process even when it is composed of plural chips.
The present invention provides a semiconductor device in which the side wall (inner peripheral surface) of the concave portion or through-hole formed in a semiconductor substrate and the side walls (outer peripheral surfaces) of the semiconductor element chip are fit to each other in their face contact; otherwise semi-conductor chips are connected with each other in the face contact of their side walls.
In this specification, (a b c), (-a -b -c), (-a -b c), (-a b -c), (a -b -c), (-a b c), (a -b c), (a b -c) are defined as the xe2x80x9csame crystal facexe2x80x9d as each other and those can be described as {a b c}. Further, (111), (-111), (1-11), (11-1), (-1-11), (-11-1), (1-1-1), (-1-1-1) are generally called {111}; therefore, e.g., (111) face and (-1-11) face are the same face as each other and are {111}.
In accordance with one aspect of the present invention, there is provided a semiconductor device having a combination of plural semiconductor chips.
Specifically, the semiconductor device with plural semiconductor chips combined according to the present invention has the plural semiconductor chips in each of which a semiconductor element is to be formed on a semiconductor substrate surface so that each element is formed on the same surface side, and has any of the following features.
(1) Plural chips are combined with their sides kept in face-contact to each other to form a sheet of wafer.
(2) Plural chips are combined with their sides having the same inclination angle kept in face-connection with each other to form a sheet of wafer.
(3) Plural chips are combined with their sides having the same crystal face kept in face-connection to form a sheet of wafer.
(4) Plural chips are combined with their sides kept in face-contact to each other to form a sheet of wafer, and a pad plate is arranged on the back surface opposite to the surface on which elements are to be formed.
(5) In item (3), the crystal face of the sides is a {111} face.
(6) In item (4), the back surface and the pad plate are bonded by bonding agent.
(7) Plural kinds of semiconductor chips are combined with their sides kept in face-contact to each other to form a sheet of wafer, and they are selected from the group consisting of chips having a central processing function, a storage function and an arithmetic function, incorporating a light receiving element and an light emitting element, having a sensor function, constituting a mere electric signal transmission means between the chips and having a movable portion, respectively.
(8) Plural kinds of semiconductor chips are combined with their sides kept in face-contact to each other, and the atoms of semiconductor material on the contact face are coupled with each other directly or through oxygen atoms.
The method for fabricating a semiconductor device according to the present invention has any of the following features.
(9) Plural chips in each of which a semiconductor element is to be formed on a semiconductor substrate surface are combined to form a sheet of wafer so that each semiconductor element is formed on the same surface side are combined, and opposite junction faces are parallel to each other.
(10) Sides of plural chips in which semiconductor elements are formed on their semiconductor substrate surface are subjected to anisotropic etching, and the etched sides are joined to connect the plural chips.
(11) In item (10), an etching solution for etching includes an alkaline solution such as KOH, NaOH, CsOH and NH4OH; an organic solution such as ethylene diamine, hydrazine, choline; and a quaternary ammonium solution such as tetramethylammonium hydroxide tetraethylammonium hydroxide.
(12) Plural chips in each of which a semiconductor element is to be formed on a semiconductor substrate surface are combined so that each semiconductor element is formed on the same surface side, and their faces for connection are bonded at temperatures of 400xc2x0 C. or more. (13) In any of items (9) to (12), an electrically conductive film is formed so that it extends over the edge of a semiconductor chip and that of another semi-conductor chip, and in accordance with the connection format of wirings, the film is cut to be divided by any of techniques of laser, ion-beam, plasma and electron beam.
(14) In any of items (9) to (12), the position of the wiring to be connected with each semiconductor chip is recognized, and the path of projecting laser light in a laser CVD device is determined so that the position does not interfere with other wirings.
(15) In any of items (9) to (12), location or its order of the wirings serving to connect plural semi-conductor chips with each other are standardized for all of the plural semiconductor chips.
In the present invention, after element chips are fabricated to have a size smaller than the conventional chip size and defect-free elements are selected, the semiconductor substrates of the selected element chips are connected with each other so that the surfaces on which the elements are to be formed are in the same surface side. This permits semiconductor devices to be fabricated within the conventional production yield.
The fabricating method according to the present invention permits many-kind small-amount production by fabricating plural kinds of element chips and changing the combination thereof in accordance with the request of a customer.
Now, the component chip means a semiconductor chip which is a component of the semiconductor device according to the present invention, and is composed of a semiconductor substrate and a surface on which an element is to be formed. The component includes concepts of both cases where the surface layer itself of the semiconductor substrate shares a semiconductor element function and another semiconductor function portion is formed on the surface of the semiconductor substrate.
The present invention provides the following meritorious effects.
(i) It is possible to fabricate large-sized semi-conductor devices without reducing their production yield.
(ii) It is possible to construct on a single chip a plurality of functions which are not inferior to that in the case of single-chip single function.
(iii) Many-kind small-amount production can be realized at low cost.
In accordance with another aspect of the present invention, there is provided a semiconductor device in which a semiconductor element chip is fit in the concave or penetrating portion (through-hole) in a semiconductor substrate.
The present invention is directed to the structure and fabrication method of a semiconductor device composed of a semiconductor substrate having at least one groove or penetrating portion with its side walls each encircled by a {111} crystal plane (hereinafter referred to as xe2x80x9csides in the {111} planexe2x80x9d) and a semiconductor element chip with its sides in the {111} plane which fits in the groove and penetration porion.
The present invention is directed to a defect relief technique of replacing a semiconductor defective element by a defect-free element chip.
In order to realize the fabricating method with high yield or defect relief technique with high reliability, a method of fabricating a semiconductor device may be used which removes, by anisotropic etching, the defective portion of a semiconductor integrated circuit element with its sides in the {111} plane formed on a semiconductor substrate, and embeds, in the removed portion, a defect-free element chip with its side walls in the same {111 } plane formed by the same etching, thereby completing a semiconductor integrated circuit.
The anisotropic etching uses the property of Si crystal that the etching speed for the {111} plane with the highest atomic density is much slower (1: several tens to several hundreds) than that for other {100} and {100} faces.
The solution having the anisotropic property for Si includes a KOH solution and ethylenediamine catechol solution. Since the angle formed by these crystal planes can be determined precisely, using e.g. the Si substrate with a {100} plane, the crystal face with an inclined {111} side wall having an angle of about 54.74xc2x0 from it can be formed.
For the above reason, if the defective portion of the semiconductor integrated circuit element formed on a semiconductor substrate is removed by anisotropic etching, an removed area with its sides in the {111} plane is formed.
The defect-free element chip with its sides in the same {111} plane formed by the same anisotropic etching is fit in the removed area to be embedded therein.
As described above, the {111} plane has been formed at a precise angle, the defect-free element chip is precisely fit in the removed area. So the element chip to be fit can be easily positioned and positioning error which the prior art involves is not generated.
If the function of a large-sized semiconductor device is divided to form small-sized element chips and the small-sized element chips are integrated to form the large-sized semiconductor device, the large-sized device can be formed with high yield.
The feature of the semiconductor device according to the present invention can be selected from any of the following items.
(16) The semiconductor device is composed of a semiconductor element chips and a semiconductor substrate having a concave portion or a penetrating portion in which the semiconductor element chip fits, and the side walls of the semiconductor element chip which constitutes at least one fitting face and those of the semiconductor element have the same crystal plane.
The concave portion or penetrating portion may be a groove or a through-hole and may be located at any position in the semiconductor substrate so that it may be located at the edge of the semiconductor substrate, and in this case, one side of the semiconductor element chip is exposed (hereinafter, this applies in the description of the specification).
(17) In item (16), the concave portion or penetrating portion has an upper shape of square, its four sides have the same crystal face, the corresponding element has an upper shape of square, and its four sides have the same crystal face.
(18) In item (16), each side of the fitting portion is a tapered face.
(19) The semiconductor device is composed of plural semiconductor elements and a semiconductor substrate having plural concave portions or penetrating portions in which the respective semiconductor elements fit, and the side walls of the semiconductor element constituting at least one fitting face of plural fitting faces and those of the semiconductor substrate have the same crystal face.
(20) In item (19), each concave portion or penetrating portion has an upper shape of square, its four side walls have the same crystal face, each corresponding element has an upper shape of square, and its four side walls have the same crystal face.
The shape is desired to be a parallelogram, but the present invention should not be limited to it; this shape may be a polygon such as a hexagon and an octagon (hereinafter, this applies in the description of the specification).
(21) In item (19), each side of each fitting portion is a tapered face.
(22) The semiconductor device is composed of a semiconductor substrate having at least one groove or penetrating portion with its sides in the {111} face, a semiconductor element with its sides in the {111} face fit in the groove or penetrating portion and a wiring of electrically connecting the semiconductor element with the semiconductor substrate.
(23) The semiconductor device is composed of a semiconductor substrate having plural groove or penetrating portions each with its sides in the {111} face, a plurality of semiconductor elements with its sides in the {111} face each fit in each of the groove or penetrating portion and a wiring of electrically connecting the semiconductor elements with the semi-conductor substrate.
(24) The semiconductor device is composed of a semiconductor substrate having plural grooves or penetrating portions, each with its sides in the {111} face, having different sizes, and a plurality of semi-conductor elements, each with its sides in the {111} face, each fit in each of the grooves or penetrating portions, and a wiring of connecting the semiconductor elements with the semiconductor substrate.
(25) In item (22), (23) and (24), the semiconductor device further includes an insulating film covering the semiconductor substrate, semiconductor element(s) and wiring.
(26) The semiconductor substrate as a component has at least one groove or penetrating portion with its sides in the {111} crystal face.
(27) The semiconductor element as a component has sides in the {111} face.
(28) The semiconductor device is composed of a semiconductor substrate having at least one groove or. penetrating portion with its sides in the {111} face, a semiconductor element with its sides in the {111} face fit in the groove or penetrating portion and the semi-conductor element is connected with the semiconductor substrate by direct bonding by thermal oxidation without using bonding agent.
(29) The semiconductor device is composed of a semiconductor substrate having at least one groove or penetrating portion with its sides in the {111} face, a semiconductor element with its sides in the {111} face fit in the groove or penetrating portion and a wiring of electrically connecting the semiconductor element with the semiconductor substrate, and the wiring connects electrodes provided on the semiconductor element and semiconductor substrate by means of wirings.
(30) The semiconductor device is composed of a semiconductor substrate having plural groove or penetrating portions each with its sides in the {111} face, a plurality of semiconductor elements each with its sides in the {111} face, each fit in each of the groove or penetrating portions, and a wiring of electrically connecting the plurality of semiconductor elements with the semiconductor substrate, and the wiring is a multi-layer inter-element wiring connecting the semiconductors with each other and covered with a multi-layer insulating film.
(31) The semiconductor device is composed of a semiconductor substrate having at least one groove or penetrating portion with its sides in the {111} face in its both front and back surfaces, a semiconductor element with its sides in the {111} face fit in the groove or penetrating portion from the front and back surfaces, a wiring of electrically connecting the semiconductor elements with the semiconductor substrate and an insulating film for covering the semiconductor substrate, semiconductor element and wiring.
(32) In item (30), an electrically conductive film is made on the side and bottom of each of the semi-conductor elements with its sides in the {111} face fit in the concave portion or penetrating portion from the front and back surfaces of the substrate so that the semiconductor elements on the front and back surfaces of the substrate are electrically connected.
(33) The defective area of the semiconductor element formed on the semiconductor substrate is removed to form at least one concave with its sides in the {111} face or penetrate through the substrate, and a defect-free element with its sides in the {111} face fit in the removed area is embedded in the removed area.
(34) In Item (33), a wiring for electrically connecting the defect-free element substituted for the defective element with the semiconductor substrate is provided, and an insulating film for covering the semiconductor substrate, semiconductor element and wiring is provided.
(35) An insulating film for an etching margin is formed between semiconductor elements on a semiconductor substrate, the defective area of each semiconductor element formed on the semiconductor substrate is removed to form at least one concave with its sides in the {111} face or penetrate through the substrate, a defect-free element with its sides in the {111} face fit in the removed area is embedded in the removed area, a wiring for electrically connecting the defect-free element substituted for the defective element with the semi-conductor substrate is provided, and an insulating film for covering the semiconductor substrate, semiconductor element and wiring is provided.
(36) Where there are plural areas of defective elements in the same substrate, the defective elements are removed to form concave each with its sides in the {111} face or penetrate through the substrate, defect-free elements each with its sides in the {111} face fit in the removed area is embedded in the removed areas, wirings for electrically connecting the defect-free elements substituted for the defective elements with the semiconductor substrate is provided, and an insulating film for covering the semiconductor substrate, defect-free semiconductor element and wirings is provided.
(37) A defective element is formed into at least one groove with its sides in the {111} face, and a defect-free element with its sides in the {111} face fit in the depth of the groove is embedded in the groove.
(38) A defective element is formed into at least one concave with its sides in the {111} face or penetrating portion from the front and back surfaces of a substrate, and a defect-free element with its sides in the {111} face fit in the concave or penetrating portion is embedded in the groove and fixed there by bonding agent from the back surface where no element area is located.
(39) A defective element of semiconductor elements formed on a semiconductor substrate is formed into at least one concave portion with its sides in the {111} face or penetrating portion, and a defect-free element with its sides in the {111} face fit in the concave or penetrating portion is embedded in the portion so that the defect-free element and the surface of the semi-conductor substrate are located at the same height.
(40) In any of items (16) to (40), the semiconductor substrate is made of a material (e.g. Si, Ge and GaAs) which can be subjected to anisotropic etching.
(41) In any of items (16) to (40), wet etching or dry etching is carried out using an etching solution such as a KOH solution and ethylenediamine catechol solution.
(42) The semiconductor substrate is removed to form at least one concave portion with its octahedral sides in the {111} face or penetrate therethrough thereby to form a semiconductor element with its sides in the {111} face fit in the removed area being octahedral, and the semiconductor element has the sides being at least one fitting face of the fitting sides and the side of the semiconductor substrate are in the same crystal face.
(43) The semiconductor substrate is removed to form at least one concave portion with its pentahedral sides in the {111} face or penetrate therethrough thereby to form a semiconductor element with its sides in the {111} face fit in the removed area being pentahedral, and one side of the pentahedron is used as a positioning face.
According to the present invention, removed areas each with its sides in the {111} face are formed on the element area of a semiconductor substrate by anisotropic etching, and semiconductor elements each with its sides in the {111} face formed by the same anisotropic etching are embedded in the removed areas.
Specifically, removed areas each with its sides in the {111} face and a different size are formed on the element areas of the semiconductor substrate, and the semiconductor elements with its sides in the {111} face in conformity with these sizes are formed and embedded in the removed areas having the different sizes. Thus, the semiconductor elements having different sizes can be simultaneously formed on one sheet of semiconductor substrate, and so custom products can be fabricated by the number requested by users.
In accordance with the present invention, in the initial stage of the substrate process, i.e., the stage when the defect occurring rate is high because of the fineness and high integration of the device, only defective areas in element areas can be removed to be easily modified. Further, if small-sized defect-free elements are previously incorporated in a substrate having grooves or through-holes each with sides in the {111} face and electric wirings are made among the elements, large-sized semiconductor elements can be fabricated with high production yield.
The semiconductor device according to the present invention provides the following representative meritorious effects.
(i) Removed areas each with its side walls in the {111} face having different sizes are formed on the element areas of the semiconductor substrate, and small-sized semiconductor elements each with its side walls in the {111} face in conformity with these sizes are formed and embedded in the removed areas having the different sizes, a large-sized semiconductor substrate can be formed.
(ii) In the initial stage of the substrate process, i.e., the stage when the defect occurring rate is high because of the fineness and high integration of the device, only defective areas in element areas can be removed to be easily modified.
For example, the following thing can be realized.
First, semiconductor elements are formed until the first wiring step by most advanced process technology. If any defective element has been generated, the corresponding area is removed and a defect-free element is arranged in the removed area. In this way, defect relief can be surely performed without deteriorating the performance of a semiconductor integrated circuit device, thereby enhancing the element production yield. Because of the effects of the above (i) and (ii), reduction in the yield of the elements due to the large-scaling and high integration of the semiconductor integrated circuit device can be restrained, and the requirement for large capacity and high grade function can be satisfied. Thus, it is possible to advance to realize the computer system by a single element.
Since defects are cured before the semi-conductor integrated circuit at the element area acquires its function and immediately after the defect has been found, defect relief with high applicability and reliability can be realized. As a result, the present invention can deal with customizing of semiconductor devices.
The fabricating method according to the present invention has the following features.
(44) In the method of fabricating a semiconductor device including plural Si substrates kept in contact with each other and of making the wiring for connecting the plural Si substrates, an electrically conductive film is formed to extend over the edge of a certain Si substrate and another Si substrate kept in contact with it, and the film is cut by laser so that it conforms with the connection format of the wiring.
(45) In the method of fabricating a semiconductor device including plural Si substrates kept in contact with each other and of making the wiring for connecting the plural Si substrates, the metallic film used for the wiring is made parallel to that of an adjacent metallic film.
(46) In item (44) or (45), the film is cut using the means selected from the group including ion beams, plasma and electron beams.
(47) In the method of fabricating a semiconductor device including plural Si substrates kept in contact with each other and of making the wiring for connecting the plural Si substrates, the position of the wiring to be connected with each semiconductor substrate is recognized, and the path of projecting laser light in a laser CVD device is determined so that the position does not interfere with other wirings. The excitation energy source should be not limited to the laser, but may be ion beams or electron beams. The wiring may be formed on the surface area of the Si substrate other than the surface area thereof where elements are to be formed.
(48) In any of items (44) to (47), a silicon oxide film or organic film is formed in the neighborhood of contact positions of the Si substrate after the Si substrates are brought into contact.
When body chips are fit into chips to be embedded, their relative positions fluctuate owing to processing variations and positioning accuracy in fitting. If an optimum wiring layout is made in accordance with the recognized state of each of the chips having fluctuation, poor connection of the wiring can be evaded. For example, if the uniform film is cut into an optimum shape in conformity with that of each chip as in the above item (44), the wiring in conformity with each chip can be surely formed.
Further, if the projection path of laser light is determined in accordance with each chip in the laser CVD technique as in the above item (47), the optimum wiring for each chip can be made.
When body chips are fit into chips to be embedded, gaps or level differences may be produced. If the film for flattening is provided as in the above item (48), the level differences can be reduced and the gaps can be embedded, thereby surely making the wiring.
The fabricating method according to the present invention (1) permits the yield of semiconductor devices to be improved and (2) permits the wiring for the semi-conductor device to be surely made, thereby improving its reliability.